This is a non-provisional application which claims priority from Korean Patent Application No. 2005-74937, filed on Aug. 16, 2005, in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.
1. FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of forming the same, and particularly, to a magnetic memory device and a method fabricating the same.
2. DESCRIPTION OF THE RELATED ART
Generally, a magnetic memory device includes two magnetic substances and a magnetic tunnel junction (MTJ) pattern including an insulating layer interposed between the two magnetic substances. The magnetic tunnel junction pattern has electric resistance varying according to magnetization directions of the two magnetic substances. The resistance in the case where the magnetization directions of the two magnetic substances are equal to each other is greater than the resistance in the case where the magnetization directions of the two magnetic substances are opposite to each other. Thus, it can be determined whether information stored in the magnetic memory device is logic “1” or logic “0” by using a voltage drop and/or a change in current amount due to such variations in resistance. The magnetic memory device is widely used because of its high speed operation, almost infinite rewritability, and non-volatility.
In general, a well-known magnetic memory cell may be programmed by magnetic fields generated from a bit line and a digit line that intersect each other. Such a magnetic memory device will now be described with reference to accompanying drawing.
FIG. 1 is a cross-sectional view of a conventional magnetic memory device.
Referring to FIG. 1, a lower interlayer oxide layer 2 is disposed on a semiconductor substrate 1, and a digit line 3 is disposed on the lower interlayer oxide layer 2. Although not shown, a MOS transistor is disposed between the lower interlayer oxide layer 2 and the semiconductor substrate 1.
An intermediate interlayer oxide layer 4 covering the digit line 3 and the lower interlayer oxide layer 2 is disposed on the semiconductor substrate 1. A lower contact plug 5 is disposed adjacent to one side of the digit line 3 to pass through the intermediate and lower interlayer oxide layers 4 and 2 and contact with the semiconductor substrate 1. The lower contact plug 5 is laterally spaced apart from the digit line 3. The lower contact plug 5 is electrically connected to source/drain regions of the MOS transistor (not shown).
A lower electrode 6 is disposed on the intermediate interlayer oxide layer 4. The lower electrode 6 is electrically connected to the lower contact plug 5, and extends laterally over the digit line 3. The digit line 3 and the lower electrode 6 are insulated from each other by the intermediate interlayer oxide layer 4.
A magnetic tunnel junction pattern 11 is disposed on the lower electrode 6. The magnetic tunnel junction pattern 11 includes a pinning layer 7, a pinned layer 8, an insulating layer 9, and a free layer 10, which are sequentially stacked. A magnetization direction of the pinned layer 8 is pinned in one direction by the pinning layer 7, and the magnetization direction of the free layer 10 may be varied. The magnetic tunnel junction pattern 11 is aligned to overlie the digit line 3.
An upper interlayer oxide layer 12 covers the lower electrode 6 and the magnetic tunnel junction pattern 11. A bit line 14 is disposed on the upper interlayer oxide layer 12 to intersect the digit line 3. The bit line 14 is electrically connected to the magnetic tunnel junction pattern 11 via an upper contact plug 13 passing through the upper interlayer oxide layer 12. The bit line 14 is aligned to overlap the magnetic tunnel junction pattern 11. That is, the magnetic tunnel junction pattern 11 is disposed at a spot where the digit line 3 and the bit line 14 intersect, and is interposed between the digit line 3 and the bit line 14.
To program data in the conventional magnetic memory device, a program voltage is applied to the bit line 14 and the digit line 3. Accordingly, a first magnetic field is generated around the digit line 3, and a second magnetic field is generated around the bit line 14. A magnetic field produced by vector production of the first and second magnetic fields is selectively applied to the magnetic tunnel junction pattern 11. Accordingly, the magnetization direction of the free layer 10 included in the magnetic tunnel junction pattern 11 is changed. Here, the magnetization direction of the pinned layer 8 is pinned by the pinning layer 7. As a result, the free layer 10 and the pinned layer 8 may have the same magnetization direction or the opposite magnetization directions. In this manner, the magnetic tunnel junction pattern 11 may store data of logic “1” or logic “0”.
The alignment between the bit line 4, the digit line 3, and the magnetic tunnel junction pattern 11 is crucial to selectively applying a constant magnetic field to the magnetic tunnel junction pattern 11 of the conventional magnetic memory device. For this reason, the alignment between the digit line 3 and the magnetic tunnel junction pattern 11, and the alignment between the magnetic tunnel junction pattern 11 and the bit line 14 are very carefully performed. As a result, a process of fabricating the magnetic memory device may become very difficult and complicated. Also, the high integration of the magnetic memory device cannot be easily achieved because sufficient alignment margins should be secured due to the several alignment operations.
Also, peripheral circuits are needed to drive the digit line 3, thereby making it more difficult to fabricate a highly integrated magnetic memory device. Also, because a program voltage through the digit line 3 is required during a program operation, the magnetic memory device increases power consumption.
In addition, the digit line 3 should be disposed under the magnetic tunnel junction pattern 11. Thus, the lower contact plug 5 laterally spaced apart from the magnetic tunnel junction pattern 11 is needed to secure a path of a current flowing through the magnetic tunnel junction pattern 11. As a result, a planar area of a magnetic memory cell may be extended.
Further, if the planar area of the free layer 10 is reduced to effect high integration of a semiconductor device, data stored in layer 10 may be lost due to a super-paramagnetic limit. For this reason, it may not be easy to reduce the planar area of the free layer 10, which consequently makes it more difficult to achieve dense integration of the magnetic memory device.
Accordingly, a need remains for a magnetic memory device and a method of fabricating the same capable of solving the aforementioned problems and other problems.